Field of the Invention
The present invention relates to a circuit configuration and a method for automatic recognition and elimination of word line/bit line short circuits in a memory cell configuration containing sensor amplifiers and having bit lines and redundant bit lines, the sensor amplifiers split the memory cell configuration into memory blocks.
Word line/bit line short circuits are known to prevent writing to and reading from a memory cell configuration in a memory. It is therefore very important to recognize and eliminate such word line/bit line short circuits in order to be able to guarantee the operation of the memory.
Such word line/bit line short circuits occur if word lines and bit lines touch one another owing to faults or irregularities during the process of manufacturing the memory, or are connected with a low impedance by conductive dirt particles, for example.
In memories which use split sensor amplifiers in the bit lines, so that each sensor amplifier is allocated two branches of a bit line or two different bit lines, and the memory cells in the memory cell configuration are split into a total of two adjacent memory blocks, it should additionally be noted that even after a bit line short-circuited with a word line in one memory block has been replaced, correct operation of the bit line in the other memory block is disrupted. This occurs because correct precharging of the bit line in the other memory block is prevented by the short circuit between the corresponding bit line and a word line in the one memory block, so that correct reading of the corresponding memory cells of the bit line short-circuited in the one memory block is no longer possible in the other memory block.
To overcome this difficulty, it is therefore not only the defective branch of the bit line in the one memory block but, in addition, also the inherently defective branch of the bit line or a different bit line in the other memory block which has hitherto been replaced by a redundant bit line in the two memory blocks. This results in the disadvantage that, in practice, twice as many bit lines have to be provided for redundancy as when only the actually defective bit lines or their branches in the respective memory blocks need to be replaced. In other words, if the bit lines which are actually disrupted by short circuits in the two memory blocks are considered, the redundancy of the existing memory cell configurations is therefore, as far as the occurrence of word line/bit line short circuits is concerned, reduced by a factor of 2 when split sensor amplifiers are used.